All SRAM devices face a potential issue of single-event upset (SEU). How do Achronix devices mitigate this problem?
As with all SRAM devices, a single-event upset (SEU) is a potential issue within the Speedcore eFPGA or Speedster FPGA. To assist users in mitigating this effect, the FPGA configuration unit (FCU) can be instructed to scrub the configuration memory (CMEM) of the FPGA or eFPGA fabric. The scrubbing feature is enabled through two levels of controls:
- Via an input pin that can act as a global strap (see details of the Speedcore Configuration User Guide UG061 for more details)
- FCU-based scrubbing registers used to determine the mode of operation. These registers are active once scrubbing is enabled via the input pin and allows for dynamic control of scrubbing.
There are three modes of operation:
- Background scan
- Background scan and repair
If scrubbing is enabled, the user must continue to supply clocks to the configuration unit even after entering user mode as the scrubbing state machine needs to be clocked continuously. When background scanning is enabled (with or without repair), the scrubbing logic continuously cycles through all configuration frames in an infinite loop. Every frame is read, and ECC bits are calculated to compare against known-good stored values. Any single-bit error can be corrected; dual-bit errors can only be detected.