Description
How do I dynamically configure GPIO delays for Speedster7t FPGAs?
Answer
GPIO delays can be configured dynamically by writing to the appropriate control and status registers (CSR). The CSR space is just one of the Speedster7t peripherals that can be accessed through the 2D NoC. The CSR space takes up a handful of the 42-bit addresses as specified in the 2D NoC global address map. As seen in table 3, chapter 6 of the Speedster7t Network on Chip User Guide (UG089), the most significant 8 bits of the CSR address must be "0010_0000".
Writing to the CSR can be accomplished by writing the API command csr_write_named in the ACE Tcl console as described in table 5 of the application note, Runtime Programming of Speedster FPGAs (AN025). Modifying CSR values can also be accomplished by utilizing NoC access points (NAPs) within the fabric as described in chapter 7, "Network-on-Chip (NoC) Primitive," of the Speedster7t Component Library User Guide (UG086).
Because the CSR can configure various NoC peripherals, the target ID field points to the handful of registers that configure the GPIO subsytems. Each GPIO subsystem has three banks. The table below lists out which GPIO banks are configured by their respective IP ID bits and the different target ID values for the different GPIO subsystems on a Speedster7t FPGA.
Each 42-bit CSR address has the following format :
Table: CSR Address Bits
| CSR Address Bits | Address Type | Possible Values |
|---|---|---|
| 41:34 | 2D NoC destination | 0010_0000 |
| 33:28 | Target ID |
|
| 27:24 | IP ID |
|
| 23:0 | Memory address | See the table below. |
Memory Addressing
The least 24 significant bits of the CSR address correspond to the different IOB configuration registers that will configure the DLLs.
Table: BLOCK Memory Addresses of GPIO Bank DLL Configuration Registers
| Register Name | Register Field | Register Field Bit Positions |
Access Type | Reset Value | Description | Address [23:0] |
|---|---|---|---|---|---|---|
| TX_DRIVE_EDGE_SEL | TX_DRIVE_EDGE_SEL | 0 | R/W | 0 | Write 1 to enable transmit data to be driven to the pad on negedge of the clock. | 24'h000020 |
| TX_DLL_ENABLE | TX_DLL_ENABLE | 0 | R/W | 0 | Write 1 to enable DLL in the transmit path. | 24'h000024 |
| RX_SAMPLE_EDGE_SEL | RX_SAMPLE_EDGE_SEL | 0 | R/W | 0 | Write 1 to sample data on fall edge of the clock in receive direction. | 24'h000028 |
| TX_FLOP_CONTROL | TX_FLOP_ENABLE | 0 | R/W | 0 | Write 1 to enable a register in the transmit path. | 24'h00002C |
| TX_PIPE_BYPASS_ENABLE | 1 | R/W | 0 | Write 1 to bypass the pipeline stage in the transmit path. | ||
| RX_DLL_ENABLE | RX_DLL_ENABLE | 0 | R/W | 0 | Write 1 to enable DLL in the receive path. | 24'h000030 |
| RX_FLOP_CONTROL | RX_FLOP_ENABLE | 0 | R/W | 0 | Write 1 to enable a register in the receive path. | 24'h000034 |
| RX_PIPE_BYPASS_ENABLE | 1 | R/W | 0 | Write 1 to bypass the pipeline stage in the receive path. | ||
| DLL_RESET | SOFT_RESET | 1 | R/W | 0 |
Write:
|
24'h000038 |
| HARD_RESET | 0 | R/W | 0 |
Write:
|
||
| SDLL0_DELAY_REG_1(†) | SDLL0_DELAY_REG_1 | 31:0 | R/W | 0 | 32-bit value programmed for delay required from slave DLL 0. The delay value will be used by DLL to set delays for the four channels, IOB pads 1 trough 4:
|
24'h00003C |
| SDLL0_DELAY_REG_2(†) | SDLL0_DELAY_REG_2 | 31:0 | R/W | 0 |
32-bit value programmed for delay required from slave DLL 0. The delay value will be used by DLL to set delays for the four channels, IOB pads 7 trough 10:
|
24'h000040 |
| SDLL1_DELAY_REG_1(†) | SDLL1_DELAY_REG_1 | 31:0 | R/W | 0 | 32-bit value programmed for delay required from slave DLL 1. The delay value will be used by DLL to set delays for the four channels, IOB pads 1 trough 4:
|
24'h000044 |
| SDLL1_DELAY_REG_2(†) | SDLL1_DELAY_REG_2 | 31:0 | R/W | 0 | 32-bit value programmed for delay required from slave DLL 1. The delay value will be used by DLL to set delays for the four channels, IOB pads 7 trough 10:
|
24'h000048 |
| SDLL2_DELAY_REG_1(†) | SDLL2_DELAY_REG_1 | 31:0 | R/W | 0 | 32-bit value programmed for delay required from slave DLL 1. The delay value will be used by DLL to set delays for the two channels, IOB pads 11 trough 12:
|
24'h00004C |
| SDLL2_DELAY_REG_2(†) | SDLL2_DELAY_REG_2 | 31:0 | R/W | 0 |
32-bit value programmed for delay required from slave DLL 1. The delay value will be used by DLL to set delays for the two channels, IOB pads 11 trough 12:
|
24'h000050 |
| SDLL3_DELAY_REG_1(†) | SDLL3_DELAY_REG_1 | 31:0 | R/W | 0 |
32-bit value programmed for delay required from slave DLL 1. The delay value will be used by DLL to set delays for the four channels, IOB pads 1 trough 4:
|
24'h000054 |
| SDLL3_DELAY_REG_2(†) | SDLL3_DELAY_REG_2 | 31:0 | R/W | 0 | 32-bit value programmed for delay required from slave DLL 1. The delay value will be used by DLL to set delays for the four channels, IOB pads 7 trough 10:
|
24'h000058 |
| MDLL_LOCK_DETECT | LOCK_DETECT | 0 | R | 0 | 1 indicates that master DLL has completed the delay calibration. | 24'h00005C |
| MDLL_LOCK_CONTROL | LOCK_COUNT | 7:0 | R/W | 0 | Number of DLL clock cycles for which lock has to be maintained. | 24'h000068 |
| LOCK_THRESHOLD | 15:8 | R/W | 0 | Number of DLL clock cycles for which phase difference has to be measured. | ||
|
Table Note † For these registers, the following equation defines the output delay: output delay = unit_cycle × 0.4 + i_delay_code/256 × unit_cycle where the unit cycle is one clock cycle
|
||||||
Configuring the GPIO Bank
In order to make use of the DLL delays, a reference clock between 300 and 500 MHz must be applied to the GPIO bank.
An asynchronous active-low reset needs to be asserted through the register "DLL_RESET". After a delay code value is written to the appropriate SDLL delay register, it will take up to 50 reference clock cycles for the DLL to lock, applying the appropriate delays to the I/O pins. In order to apply the delays on the receive path, the least significant bit of the value stored in register RX_DLL_ENABLE must be set to 1. In order to apply the delays on the transmit path, the least significant bit of the value stored in register TX_DLL_ENABLE must be set to 1.
Pipeline Registers
Receive Path
The figure below illustrates the data path of the data inputs from the GPIO pad to the FPGA fabric.
Figure: Data Path for GPIO Inputs on the Receive Path
As seen above, the delayed data will be registered by the pipeline flops in the GPIO bank. The configured delay is applied to the receive signal. When registering the signal in the GPIO bank, it is observed at zero to one clock-cycle delay from the fabric.
In order to observe the receive DLL delays on the fabric as described in the output delay equation, the receive flops must be disabled by writing the value x00000000 to register RX_FLOP_CONTROL.
Transmit Path
The figure below illustrates the data path of the data outputs from the FPGA fabric to the GPIO pad.
Figure: Data Path for GPIO Outputs on the Transmit Path
As seen above, the delay is applied after the registers in the GPIO bank and are applied directly to the device output pads. Therefore, the delayed data as described by the output delay equation can be observed on the output pads regardless of whether the pipeline flops are enabled or not.