Description
I want to design a PCB for the AC7t1500 device and need some basic information.
Answer
Below are some frequently asked questions along with answers. For further information, contact support@achronix.com.
What is the package for the Speedster7t FPGA AC7t1500?
The AC7t1500 is delivered in a flip-chip ball grid array (FCBGA).
What are the package dimensions, pin count and package ball pitch size?
The package size is 52.5 mm × 52.5 mm and has sixteen layers. The device has 2597 pins and has a homogeneous ball pitch of 1 mm.
Do you have PCB material recommendations for board design?
The following table shows the recommended choice of laminate materials:
| Material | Manufacturer | Country of Origin | Dk (Dielectric Constant) |
Df (Loss Tangent) |
Measured Frequency |
Tg (Glass Transition Temperature) |
|---|---|---|---|---|---|---|
| Tachyon 100G | ISOLA | China | 3.02 | 0.0021 | 20 GHz | 180°C |
| Megtron 7N | Panasonic | Japan | 3.4 | 0.0020 | 12 GHz | – |
| Megtron 6N | Panasonic | Japan | 3.4 | 0.0040 | 12 GHz | – |
| IT-988GSETC | ITEQ | Taiwan | 3.24 | 0.0015 | 10 GHz | 180°C |
| CLTE-XT | Arlon | USA | 2.94 | 0.0012 | 10 GHz | – |
This laminate survey was done to look for a material appropriate for the high-density interconnect (HDI) buildup structure for our validation boards, which was necessitated due to the onboard GDDR6 memories. We have chosen Tachyon 100G based on our requirements. If the user is not planning to utilize GDDR6 memories, then the search criteria and construction could be different.
What is the structure of the board stack-up?
We have used a 5-N-5 HDI construction for our validation and characterization platforms. The top and bottom five layers are HDI with laser vias. The core has ten standard stack-up layers. This structure was chosen to support the following:
- Route SerDes receive and transmit layers separately with a ground plane in between to minimize near-end cross-talk
- Laser vias do not have a stub, so there is no resonance
Where do I find the power requirements for Speedster7t FPGAs?
The details of the power requirements can be found in the Speedster7t Power User Guide (UG087). The user can also calculate power consumption for interfaces their design ad application require by utilizing the Speedster7t Power Estimator User Guide (UG093).
Are there power sequencing requirements for Speedster7t FPGAs?
Yes, there is only a single power sequencing requirement for Speedster7t family of devices. The VCC (0.85V) power supply should be brought up before the EFUSE_VDD2 (1.8V) and pulled down after EFUSE2_VDD2 is pulled down. This sequencing is to ensure that there is no unwanted leakage when powering up the device.
Where can I find the pin connections for the Speedster7t FPGA?
The Speedster7t pin connectivity user guide can be downloaded: Speedster7t Pin Connectivity User Guide (UG084)
Is a reference board schematic available?
The schematic of our memory, Ethernet, and PCIe (MEP) characterization board can be found on our secure portal: Board Schematics (login required).
Where can I find the Speedster7t1500 pin table and package ball map?
The device pin table can be found on our website: Speedster7t 7t1500 Pin Table.