I have a reset signal that routes to many endpoints in my design, and sometimes this can cause timing issues because of the high fan-out on reset. Is there some way to route the reset signal on the clock network?
Generally it is recommended to reduce the number of logic elements that need to be reset by taking advantage of initial values and coding in such a way that reset is only needed on a few end points. If this method is not possible, and a reset signal is required to route to many end points in the design, the user can opt for a method that allows the reset signal, or other high fan-out signal, to route on the clock network.
Using Reset within Fabric Only
If clocking resources are not in short supply, and the reset fan-out is high, the designer can route reset on a clock network. This method frees up precious data interconnect resources and provides a balanced way to route reset to numerous destinations. In addition, this method allows for routing reset to many locations without needing to duplicate reset logic or manually instantiate a reset tree. One potential drawback is that the reset signal will incur larger insertion delay once it is placed on the clock network. Depending on the size of the Speedcore eFPGA or Speedster FPGA instance, the insertion delay of reset can be large and can impact timing. The following describes several options when routing reset on the clock network. Depending on the particular design, some of these options may be more successful than others.
To route a reset signal on a clock network, set a constraint in the design's PDC file.
Below are examples of two possible constraints that can be used to route reset on a clock network. In practice, a designer only needs to choose one of these constraints, whichever is appropriate for their design.
For more information and details on routing a high fan-out signal on the clock network, please refer to the application note Routing Reset Signals on Speedcore eFPGAs (AN007).