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Achronix
Tools

Tools

A collection of articles on topics ranging from synthesis, constraints, placement, routing, timing, GUI, and more.

Synthesis

How Do I Infer an LRAM for Speedcore eFPGA Designs?
How Do I Infer an LRAM2K_SDP for Speedster7t Designs?
How Do I Infer a BRAM72K_SDP for Speedster7t Designs?
Does ACE Support Netlists Created by Yosys Synthesis Tool?

Constraints, Attributes, and Options

How Do I Control Buffer Insertion in ACE?
How Do I Control Fan-Out on a Specific Signal?

Routing

How Do I Debug a Routing Error in ACE?
How Do I Route a High Fan-out Net Like Reset on the Clock Network?

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