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A collection of articles on topics ranging from synthesis, constraints, placement, routing, timing, GUI, and more.

General

  • What Changes Will Accompany the RHEL/CentOS 6 End of Life?

Synthesis

  • How Do I use Synthesis Directives to Infer Different Types of RAMs in a Speedster7t FPGA?
  • Inferring LRAMs and BRAMs via Memory Arrays on Speedster7t FPGAs
  • I am Getting the Error "The license key and data feature do not match" with the Latest Release of Synplify Pro
  • How Do I Infer an LRAM for Speedcore eFPGA Designs?
  • How Do I Infer an LRAM2K_SDP for Speedster7t Designs?
  • How Do I Infer a BRAM72K_SDP for Speedster7t Designs?
See all 7 articles

Constraints, Attributes, and Options

  • Best Practices for Related Clocks in Speedster7t Devices
  • How Do I Control Buffer Insertion in ACE?
  • How Do I Control Fan-Out on a Specific Signal?

Routing

  • How Do I Debug a Routing Error in ACE?
  • How Do I Route a High Fan-out Net Like Reset on the Clock Network?
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