Description

I am trying to apply fan-out control on certain signals using RTL level attributes, for example, in VHDL and Verilog code:

--! VHDL version
SIGNAL state_signal : std_logic_vector(31 downto 0);
ATTRIBUTE syn_maxfan of state_signal " SIGNAL is "8"

// Verilog version
logic [31:0] state_signal /* synthesis syn_maxfan=8 */;

I have also tried setting constraints in an FDC file when compiling in Synplify Pro, for example:

define_attribute {state_signal} syn_maxfan 8

When compiled in ACE, these fan-out constraints are not being honored. How can I control signal fan-out all the way through ACE? Does forward annotation of constraint files need to be enabled?

Answer

As the Achronix design flow uses two tools, one for synthesis and one for place and route, it is necessary to use two attributes to control fan-out.

The attribute syn_maxfan is only recognized by Synplify Pro, which then applies the attribute to the netlist. Upon reading the netlist, ACE applies only its own fan-out algorithms. For ACE, the relevant attribute is fanout_limit.  This constraint must be applied during the ACE run using a PDC file.

For the example signal above, the following is needed in the PDC file.

set_property fanout_limit 8 [find {*state_signal*} -nets]

Productivity Tip

To test a .pdc file within ACE, perform Run Prepare only (right-click on the flow and select Run Selected Flow Step). This action reads in the netlist and performs any re-synthesis. The next step is to then experiment with the find command in the Tcl console to ensure you have the correct search string. 

Achronix recommends using a trailing wildcard as both Synplify Pro and ACE can add suffixes to a signal (state_signal_ret, state_signal_z1, etc.). Once you have proven the search string, add it to the project PDC file. When Run Prepare is now run, the log displays whether fanout_limit has been successfully applied to the net.

The fanout_limit attribute is described in the ACE Users Guide, under Concepts → Advanced Concepts → ACE Verilog Attributes.

Note: For any signal that has a fan-out limit applied, ACE inserts buffers to replicate the signal and reduce the fan-out. To understand how these limits are applied, and how to manage them, refer to How Do I Control Buffer Insertion in ACE?