I have two clocks in my design for a Speedster7t device that are related to each other. How should I configure my clocks to ensure the design works as expected?
In Speedster7t devices, the outputs from any PLL must be considered to be asynchronous to each other. If a design requires two clocks to be related, for example, a divide-by-two clock, Achronix recommends to use the ACX_CLKDIV primitive. The ACX_CLKDIV primitive allows for divide by 2, 4, 6, and 8. Designers need to instantiate the ACX_CLKDIV in their RTL as well as add the proper constraint for the generated clock. Below is an example of the Verilog instance of the ACX_CLKDIV followed by the corresponding SDC timing constraint.
// Declare the output clock from the ACX_CLKDIV
// Use syn_keep so that the net retains its name in the output netlist. This is necessary for the associated SDC constraint to be applied in ACE
logic clk_in_div_2 /* synthesis syn_keep=1 */;
.div_by ( 2 ),
.offset ( 0 )
) x_ACX_CLKDIV_clk_in (
# Example of constraint required with divide by 2, and offset of 0. Input clock is from the port "i_clk_in". Output of divider connects to net named "clk_in_div_2"
create_generated_clock -name clk_div_2 -source [get_port i_clk_in] -divide_by 2 [get_nets clk_in_div_2]
Note: The SDC constraint should be added into both the Synplify Pro constraints file (
/src/constraints/synplify_constraints.sdc in Achronix example designs), and also the ACE constraints file (
/src/constraints/ace_constraints.sdc in Achronix example designs).
For more details on using the ACX_CLKDIV primitive, refer to the Clock Functions chapter in the Speedster7t Component Library User Guide (UG086).