Description
I have two clocks that are configured as outputs of PLLs in a Speedster7t FPGA, and I am seeing the following error:
ERROR: Paths between clocks <clk1> and <clk2> cannot be timed accurately due to unknown values of skew and/or phase relationships
What does this error mean, and how can I fix it?
Answer
This error occurs because all PLL outputs in a Speedster7t FPGA must be considered asynchronous (including multiple outputs from a single PLL), and ACE has found a logic path that is shared between the two clocks (the path crosses from one clock domain to the other). When two clocks are asynchronous and also share a logic path, it is required for users to declare the clocks to be asynchronous to each other in the design SDC timing constraints file. Additionally, the design must include proper clock domain crossing logic such as synchronizers. The following is an example of the constraint needed in an SDC file to eliminate this error:
set_clock_groups -asynchronous -group {clk1} \
-group {clk2}
This constraint explicitly sets the two clocks as asynchronous to each other so that ACE does not time paths between them. ACE instead assumes the design has implemented proper clock domain crossing logic on any logic paths between the two clock domains.
If the design requires the clocks to be related, for example divide by two, Achronix recommends using the ACX_CLKDIV primitive in the design to generate the second related clock. For more details on this, refer to Best Practices for Related Clocks in Speedster7t Devices.