How Do I use Synthesis Directives to Infer Different Types of RAMs in a Speedster7t FPGA?

Description

How can I direct Synplify Pro to infer the type of RAMs I want when targeting a Speedster7t FPGA?

Answer

It is possible to synthesize memory elements into predetermined types of RAM via RTL directives or by adding in an FPGA design constraint (FDC) file to your Synplify Pro project. This file is used to apply non-timing and non-placement constraints to the design.

RTL Directives

Synthesis directives can be applied to individual entities in the RTL. The following memory array declaration generates a structure using BRAMs.

reg [DATA_WIDTH - 1:0] mem_array [DEPTH] /* synthesis syn_ramstyle = block_ram*/ ;

The following memory array declaration generates structures using LRAMs.

reg [DATA_WIDTH - 1:0] mem_array [DEPTH] /* synthesis syn_ramstyle = logic_ram*/ ;

The following memory array declaration generates structures using registers.

reg [DATA_WIDTH - 1:0] mem_array [DEPTH] /* synthesis syn_ramstyle = registers*/ ;

Constraints File

An FDC can be added to any Synplify Pro project to direct the tool to generate particular types of RAMs. Sometimes, a designer may want to synthesize a design with only one type of memory cell. The following synthesis directive generates all memory modules in a particular project using BRAMs.

define_global_attribute {syn_ramstyle} {block_ram}

The following synthesis directive generates all memory modules in a particular project using LRAMs.

define_global_attribute {syn_ramstyle} {logic_ram}

The following synthesis directive generates all memory modules in a particular project using registers.

define_global_attribute {syn_ramstyle} {registers}

Often, a designer may only want some of the memory modules within the design to be synthesized using specific cells, allowing the synthesizer to decide how the rest of the memory elements within that design are synthesized. The following synthesis directive finds each instance of a particular memory module and synthesizes it accordingly.

foreach inst [c_list [find -hier -view MODULE_NAME*]] {
  define_attribute $inst {syn_ramstyle} {RAM_TYPE}
}

The following RAM_TYPE values synthesize BRAMs, LRAMs, and registers respectively:

• block_ram
• logic_ram
• registers

Overriding Number of Available RAM Resources Within the Device

Sometimes, designers want to utilize less of the available LRAMs or BRAMs in the device, such as when the design being built is intended to be used as a partition within a larger design.

The following synthesis directive changes the number of available memory resources within a design.

define_global_attribute {syn_allowed_resources} {RAM_TYPE = CUSTOMIZED_LIMIT}

Note: The values in the RAM_TYPE field are different than the ones specified for syn_ramstyle. The CUSTOMIZED_LIMIT field maximum value varies based on the device being used as seen in the table below.

Table: CUSTOMIZED_LIMIT Field Maximum Values