Description

Which synthesis tools generate valid netlists for ACE? How do I use ACE with Yosys, the open source synthesis tool?

Answer

Achronix partners closely with Synopsys to ensure support with their Synplify Pro synthesis tool. It is recommended to use Synplify Pro to synthesize RTL designs, as this generates known valid netlists for ACE. However, that does not mean ACE does not accept valid netlists generated from other synthesis tools. ACE can use a netlist generated from any tool as long as it follows these simple guidelines:

• Generate a structural Verilog netlist consisting of ACE's library primitives.

Note: Primitives are device-specific. The library can be found in
<ACE_install_dir>/libraries/<device_family>/syn/<device_family>_user_macros.v.
For example, the AC7t1500 primitives can be found in 
<ACE_install_dir>/libraries/speedster7t/syn/speedster7t_user_macros.v.

• The netlist must have the following comment when not using Synplify Pro to generate the netlist.

  // Netlist not written by Synplify