How Do I Configure Integrated Synthesis with ACE 10.0

Description

I have a design that runs successfully on ACE 9.2.1 (or older version of ACE), and I want to upgrade it to ACE 10.0, which enables integrated synthesis.

How can I successfully configure integrated synthesis with ACE 10.0?

Answer

There are two different methods to successfully configure integrated synthesis with ACE 10.0.

Method 1: Import the Existing Synthesis Project

An existing synthesis project can be imported to ACE 10.0 allowing ACE to automatically load the source and constraints files. Follow these steps to import an existing Synthesis project:

1. Launch ACE 10.0 and load the existing ACE 9.2.1 (or older ACE version) project.

2. A dialog box appears with the option to change the implementation settings to the device-specific default for ACE version 10.0.

   Choose Reset All Impl Options.

    

   

   Figure: Resetting All Impl Options

    

3. Import the existing synthesis project by navigating to Actions → Synthesis → Import Synplify Project, as shown.

    

   

   Figure: Importing the Existing SynplifyPro Project

    

   Note: Normally, for Achronix designs, SynplifyPro projects exist in the src/syn/<design>.prj directory.

4. Ensure the top module name is properly set. If not, add the top module name where shown.

    

   

   Figure: Ensuring the Top Module Name

    

5. The include path relative to the ACE Project is automatically set from the existing SynplifyPro project. Modify as needed by navigating to Options → HDL Include Path. Achronix designs normally set the include path to ../include.

    

   

   Figure: Adding the HDL Include Path

    

   Note: If the project has any HDL defines, add them to the top-level options.

6. Remove the old standalone synthesis netlist file by navigating to Place and Route → Netlists → <name> → Remove.

    

   

   Figure: Removing the Old Standalone Synthesis Netlist File.

    

7. Regenerate all IORING files.

8. Run Synthesis by navigating to Flow → Synthesis → Run Selected Flow Step.

    

   

   Figure: Running Synthesis

Method 2: Manually Add the Synthesis

Follow these steps to manually add the synthesis project:

1. Launch ACE 10.0 and load the existing ACE 9.2.1 (or older ACE version) project.

2. A dialog box appears with the option to change the implementation settings to the device-specific default for ACE version 10.0.

   Choose Reset All Impl Options.

    

   

   Figure: Resetting All Impl Options

    

3. Add all RTL files by navigating to Source → RTL → Add RTL Files as shown.

   Ensure that the default_netype.v file is placed at the top and that the top-level RTL file is placed at the bottom of the list.

    

   

   Figure: Adding RTL Files

    

   Note: The correct order of RTL files is crucial in synthesis projects as it determines the sequence in which files are read and applied. Placing the default_nettype.v file first is recommended to ensure the proper pre-declaration of nets and wires. It is advisable to place the top-level module last, as the project assumes the last file as the top-level file when the top module name is not set.

4. Add synthesis constraints files by navigating to Source → Synthesis → Constraints → Add Synthesis Constraint Files as shown. It is recommended to place the .sdc file before the .fdc file.

    

   

   Figure: Adding Synthesis Constraints Files

    

5. Ensure the top module name is properly set. If not, add the top module name as shown.

    

   

   Figure: Ensuring the Top Module Name

    

   Note: By checking the Auto-Select Top Module box, the last file placed in the order of RTL files is selected as the top-level RTL file.

6. Set the include path relative to the ACE project by navigating to Options → HDL Include Path as shown. Achronix designs normally set the include path to ../include.

    

   

   Figure: Adding the HDL Include Path

    

   Note: If the project has any HDL defines, add them to the top level options.

7. Remove the old standalone synthesis netlist file by navigating to Place and Route → Netlists → Remove.

    

   

   Figure: Removing the Old Standalone Synthesis Netlist File

    

8. Regenerate all IORING files.

9. Run Synthesis by navigating to Flow → Synthesis → Run Selected Flow Step.

    

   

   Figure: Running Synthesis

Environment Variables

For integrated synthesis, it is important to define the location of the SynplifyPro executable file.

1. In Linux, the location of the SynplifyPro executable file is defined using the SYNPLIFY_HOME environment variable. This variable points to the installation directory for SynplifyPro. The /bin directory that contains the SynplifyPro executable should be within the SYNPLIFY_HOME directory. Use the following commands to set up the environment variables.

   From bash:

   $ export SYNPLIFY_HOME=<local_path>/synopsys/SynplifyPro/U-2023.03X-2

   From csh:

   $ setenv SYNPLIFY_HOME <local_path>/synopsys/SynplifyPro/U-2023.03X-2

   In Windows, the location of SynplifyPro is defined using the ACX_SYNPLIFY_TOOL_PATH environment variable. This variable points to the actual .exe executable file.

    

   

   Figure: Environment Variables for Windows

    

2. After setting the environment variables, restart ACE to load the environment variables into the tool during startup.