How do I Convert an Achronix Speedster Customer Design to a New Device? – Achronix

Description

I have an Achronix customer design that is targeted to a particular Speedster7t FPGA. However, I have a different Speedster7t FPGA on my target hardware. How do I convert an Achronix customer design to a different Speedster7t FPGA?

Answer

Overview

The following is an overview of the recommended process for converting an Achronix customer design to a different Speedster7t FPGA.

Update the hard IP configuration (.acxip) files. Besides changing the FPGA, it might be necessary to enable specific I/O pins, or specify performance limits.
Port batch flow makefiles.
Generate new /src/ioring IP files.
Port Synplify and ACE GUI project files.
Add any necessary RTL changes (some Speedster7t FPGAs require including soft IP macros at the top level).
Perform device builds using both the batch flow and the GUI flows.
Add new device support to the top level testbench.

Example

The following example shows how to convert a Speedster7t AC7t1500 design to a Speedster7t AC7t1450 design. Other design conversions would follow a similar path.

In each file in the /src/acxip directory, change the target_device field from AC7t1500 to AC7t1450.

In the /build directory, edit Makefile and change the DEVICE value. If necessary, change the SPEED_GRADE and PACKAGE as well:

# ------------------------------
# If targeting a Speedster7t device, enable the lines below
# ------------------------------
# 2 devices currently supported; AC7t1500, AC7t1450
DEVICE     := "AC7t1450"
DEVICE_ACE := $(DEVICE)
PACKAGE    := "F53"
# ------------------------------
# Set desired Speed Grade
# ------------------------------
SPEED_GRADE := "C2"

Optionally, if it is desired to identify the AC7t1450 build separately from the AC7t1500 build, also edit the recipe in the make file that performs the final bitstream copy, adding in the version values. In the following example, the suffix _1450 is added to the filename, prior to the version values, during the copy command.

# Make copy_bitstream use wildcards to copy any hex, flash or pcie file to the output bitstream folder, with version number
# Make dependent upon ACE hex file generation
### For the copy command, add _1450 to the copied bitstream name.
.PHONY : copy_bitstream
copy_bitstream : $(ACE_BUILD_DIR)/$(IMPL_DIR)/output/$(TOP_LEVEL_MODULE).hex
    @for EXT in hex flash pcie; do \
        for PROG_FILE in `find $(ACE_BUILD_DIR)/$(IMPL_DIR) -name "*.$$EXT"`; do \
            BASE_NAME=$$(basename -- $${PROG_FILE%.*}); \
            cp $(ACE_BUILD_DIR)/$(IMPL_DIR)/output/$$BASE_NAME.$$EXT $(OUTPUT_BITSTREAM_PATH)/$$BASE_NAME\_1450.$(MAJOR_VERSION).$(MINOR_VERSION).$$EXT ; \
            echo "Copied $$BASE_NAME.$$EXT to $(OUTPUT_BITSTREAM_PATH)/$$BASE_NAME.$(MAJOR_VERSION).$(MINOR_VERSION).$$EXT" ; \
        done \
    done

In the /build directory, execute the following:
```
> make clean
> make ioring_only
```
If the generation fails, review the error message (particularly in the case of the AC7t1450 FPGA), to observe whether the required SerDes bandwidth is greater than that supported by the device. In this instance, it is necessary to lower the total SerDes bandwidth across the whole design. Often the easiest approach is to reduce PCIe from a x16 to a x4 lane configuration. It may be necessary to iterate over a number of hardened IP configurations until one is found that meets the performance limits of the device.
In the /src/syn/<project name>.prj Synplify Pro GUI project file, change the -part option to AC7t1450. If necessary, change the -speed_grade and -package options as well:
```
#device options
set_option -part AC7t1450
set_option -package F53
set_option -speed_grade C2
```

In the same file, change the Synplify configuration file to AC7t1450_synplify.sv:

#project files
add_file -verilog -vlog_std sysv {$ACE_INSTALL_DIR/libraries/device_models/AC7t1450_synplify.sv}

In the /src/ace/<project name>.acxprj ACE GUI file, change the partname to AC7t1450. If necessary, also change the speed_grade and package options as well:

# Implementations
# impl_1
create_impl -not_active -project  impl_1
set_impl_option -project   -impl impl_1 -- partname "AC7t1450"
set_impl_option -project   -impl impl_1 -- package "F53"
set_impl_option -project   -impl impl_1 -- speed_grade "C2"

In the same file, change the flow mode to evaluation:
```
set_impl_option -project  -impl impl_1 flow_mode "evaluation"
```
Note: The previous two instructions refer to editing the ACE GUI project. If preferred, the existing project can be opened in the ACE GUI, and the above settings changed in the Projects Perspective → Options → Design Preparation tab.

The AC7t1450 FPGA has design requirements for two soft macros to be included in the design. To instantiate these blocks, add the following to the /src/rtl/<project name>_top.sv source file. The following code example shows a design that can be compiled for multiple devices, including the AC7t1450 FPGA. If the design is only intended for the AC7t1450, the `ifdef and `endif constructs can be removed.

// ----------------------------------------------------------------------
// Support for the AC7t1450 device
// ----------------------------------------------------------------------
// If this design is intended to be targeted to the AC7t1450 device,
// then it is necessary to instantiate two macro cores in the fabric.
// The first core is the cryptographic core. If unrequired for an AC7t1450 design,
// then instantiate a bypass instance of the core as shown below.
// The second cores is the SRM, (Serial Rate Monitor).  This must also be
// instantiated in all AC7t1450 designs, as shown below
// ----------------------------------------------------------------------
// The define ACX_DEVICE_AC7t1450 is set as follows :
//      In simulation by $ACE_INSTALL_DIR/libraries/device_models/AC7t1450_simmodels.v
//      In synthesis by  $ACE_INSTALL_DIR/libraries/device_models/AC7t1450_synplify.v
//
//      For this design the above files are selected as follows
//      In simulation, in the appropriate /sim//Makefile
//      In GUI build flow, the synthesis project file in /src/syn, (in conjunction with changing the -part option).
//      In batch build flow, the selection is done in /scripts/create_syn_project.tcl based on the selected device
// ----------------------------------------------------------------------
`ifdef ACX_DEVICE_AC7t1450
    ACX_AESX_GCM_K_BYPASS x_ACX_AESX_GCM_K_BYPASS ();
    (* must_keep *) ACX_SRM x_ACX_SRM () /* synthesis syn_noprune=1 */;
`endif

In the /src/constraints directory, edit ace_options.tcl to set the ACE flow mode to Evaluation:
```
# -------------------------------------------------------------------------
# Option to set flow mode.
# Currently set to evaluation as no bitstream generation, for this device, at this time
# -------------------------------------------------------------------------
set_impl_option  flow_mode  "evaluation"
```
Note: This is a temporary step as current ACE releases do not support bitstream generation for the AC7t1450 device. Future ACE releases are to support bitstream generation at which point this step can be ignored. Confirm whether the target device has bitstream generation supported in the ACE release you are using. If not, change the flow mode to Evaluation.
In the /build directory, execute the following:
```
> make clean
> make run
```
This performs a batch build, creating the place-and-routed design for the AC7t1450 FPGA.
In the /src/syn directory, open the Synplify Pro GUI project and select Run. It is now possible to synthesize an AC7t1450 netlist.
In the /src/ace directory, open the ACE GUI project. This should now be set to the AC7t1450 FPGA, with the netlist from the preceding step. It is now possible to run place and route on the AC7t1450 design.

In the /src/tb directory, open the top level testbench file and add AC7t1450 DSM support as follows:

// Include the appropriate DSM utility file which defines the appropriate macros
// If unsupported device selected, then compilation will fail
`ifdef ACX_DEVICE_AC7t1500
  `include "ac7t1500_utils.svh"
`elsif ACX_DEVICE_AC7t1450
  `include "ac7t1450_utils.svh"
`else
  `include "unknown_utils.svh"
`endif

Add conditional support for any signals that may change between the AC7t1500 and AC7t1450 designs:

// PCIe LTSSM state.  Different signal per design
`ifdef ACX_DEVICE_AC7t1500
    logic [5:0]             pci_express_x16_status_ltssm_state;
`elsif ACX_DEVICE_AC7t1450
    logic [5:0]             pci_express_x4_status_ltssm_state;
`endif

In the /sim/<simulator> directory, edit the Makefile to specify the correct device:

# Define the target device
# Two devices currently supported; AC7t1500, AC7t1450
DEVICE     := AC7t1450

In the /sim/<simulator> directory, it should now be possible to execute "make run" and have the simulation complete the targeting of the AC7t1450 FPGA:
In the /sim/questa directory, edit the qsim_<design name>.do Questa command file and change the device value:
```
# 2 devices currently supported; AC7t1500 and AC7t1450
quietly set DEVICE "AC7t1450"
```
In the /sim/questa directory, it should now be possible to execute "vsim -do qsim_<design_name>.do" and have the simulation run targeting the AC7t1450 FPGA.

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