Description
What are Speedster®7t special-purpose I/O (SPIO), and how do they differ from general-purpose I/O (GPIO)?
Answer
Caution! SPIO are currently not supported in ACE; however, this article will be updated for future ACE releases.
The DDR4 subsystem in the Speedster7t AC7t1500 can be set in DDR4 PHY bypass mode or regular PHY mode. In the bypass mode, the user can access all DDR4 I/O as SPIO and utilize it in their design. Or, they can utilize the DDR4 I/O in regular PHY mode for DDR4 memory interfacing, but a combination of both is not allowed. The support for these SPIO differ from our standard GPIO. The table below outlines the major differences:
Table: Support Specifications for GPIO vs SPIO
| Feature | GPIO | SPIO |
|---|---|---|
| Availability | Dedicated GPIO are always available. | Only available when the DDR4 interface is not exercised, and the DDR4 PHY is set in bypass mode. |
| Max frequency |
The dedicated GPIO operate at a maximum rate of 500Mhz |
These I/O are meant to drive low-frequency interfaces for test/debug purposes such as boundary scan, DC I/O parametric testing, SoC-level ATPG I/O, DDR4 memory connectivity testing, etc., running at a maximum of 100 Mhz(†) |
| Supported I/O standards | Supports multiple I/O standards (refer to the table, I/O Standard Support for GPIO, below) | Not compliant with any official I/O standard. These I/O work at 1.2V ±5% (with provision of certain on-die termination schemes) |
| Signal direction | Can be configured as either input or output signals | The direction of these pins is retained from that of the DDR4 interface. |
| Total count | 64 (bidirectional) | 157 (110 bidirectional, 47 outputs only) |
|
Table Note: † It is difficult to determine the maximum rate since these are not clock paths but rather combinatorial paths. The maximum frequency depend on user logic in the fabric, board-level skews and delays. In general, these I/O can operate up to 100 MHz. |
||
Table: I/O Standard Support for GPIO
| I/O Standard Supported | Supported Voltage (V) |
Type |
|---|---|---|
| HSTL Class I | 1.5 | Single-ended, differential |
| 1.8 | ||
| HSTL Class II | 1.5 | |
| HSUL | 1.2 | |
| LVCMOS | 1.1 | |
| 1.2 | ||
| 1.5 | ||
| 1.8 | ||
| SSTL Class I | 1.2 | |
| 1.35 | ||
| 1.5 | ||
| 1.8 | ||
| SSTL Class II | 1 |
Device Port Assignments in ACE
The table below shows how the user-defined signals and associated ports can be utilized for GPIO:
Table: GPIO Pin Support on AC7t1500
| I/O Instance Name | Device Port Name | Type |
|---|---|---|
| <user_defined_ports> | GPIO_[N0/S0]_BYTE[1:0]_BIT_[11:0] | Bidirectional |
| <user_defined_ports> | GPIO_[N0/S0]_BYTE2_BIT_[7:0] |
The following table lists the SPIO pins on the Speedster7t AC7t1500:
Table: SPIO Pin Support on AC7t1500
| Pin Name | Type |
|---|---|
| DDR4_S0_A17 | Output |
| DDR4_S0_ACT_N | |
| DDR4_S0_A_[13:0] | |
| DDR4_S0_BA_[1:0] | |
| DDR4_S0_BG_[1:0] | |
| DDR4_S0_BP_ALERT_N | Bidirectional |
| DDR4_S0_BP_MEMRESET_L | Output |
| DDR4_S0_BP_VREF | Bidirectional |
| DDR4_S0_BP_ZN | Output |
| DDR4_S0_CAS_N | |
| DDR4_S0_CID_[2:0] | |
| DDR4_S0_CKE_[3:0] | |
| DDR4_S0_CK_[N/P]_[3:0] | |
| DDR4_S0_CS_N_[3:0] | |
| DDR4_S0_UDQS_N_[8:0] | Bidirectional |
| DDR4_S0_DQ_[8:0]_[7:0] | |
| DDR4_S0_LDQS_[N/P]_[8:0] | |
| DDR4_S0_ODT_[3:0] | Output |
| DDR4_S0_PAR | |
| DDR4_S0_RAS_N | |
| DDR4_S0_DM_DBI_UDQS_P_[8:0] | Bidirectional |
| DDR4_S0_WE_N | Output |