I want to use the NoC in my AC7t1500 design. How does the NoC handle transaction arbitration?
The Speedster7t network on chip (NoC) handles all transaction arbitration within the NoC logic itself. There are two arbitration schemes designed to prevent deadlock and treat endpoints with fairness. The rows and columns use a configurable round-robin arbitration scheme, and the peripheral portion of the NoC uses a FIFO-based arbitration scheme.
Rows and Columns with Configurable Round-Robin
The NoC handles transaction arbitration internally, and interleaves traffic from AXI transactions, Ethernet packets, and/or data streaming. This arbitration not only keeps traffic moving and prevents backups, but also keeps the NoC operating at its peak capacity. The rows and columns use a configurable round-robin arbitration scheme, where the user can configure the arbitration schedule at each NAP. The schedule values are passed via parameters when the NAP is instantiated and remain static after configuration of the fabric. For the NAPs on columns, there is a parameter for the north-to-south direction as well as the south-to-north direction. Similarly, the rows have a parameter for the east-to-west direction as well as west-to-east.
Each arbitration parameter is a 32-bit value used to initialize the arbitration schedule mechanism. Bit 0 of the arbitration schedule vector is used to determine if the local NAP transaction entering the NoC wins arbitration when there is competing traffic from the upstream NAP on the row or column. If bit 0 has a value of '
1', the local traffic entering the NoC wins, while if bit 0 has a value of '
0', the upstream transaction on the row or column wins. After each NoC clock cycle where both the local transaction and the upstream transaction are competing for access, the value in the schedule register rotates to the left. For example, a value of
32'hAAAA_AAAA means that the local NAP transaction has high priority on every second NoC cycle.
The figure below shows a local transaction initiating from the FPGA logic trying to enter the NoC through a NAP slave, while an upstream transaction is traversing the row at the same time. If there are no competing transactions during that NoC clock cycle, the transaction passes through the NAP without any arbitration.
Figure: NAP Arbitration
ACE chooses default values for the arbitration schedule to create fairness on the rows and columns, but a user can override those values if a particular NAP needs to have higher priority in a design. It is recommended that users do not override the arbitration schedule values, as the default values set fairness for all NAPs on a row or column. The default value for each NAP is based on the number of instantiated NAPs along a row or column, and the location of the particular NAP. The formula used for the values on each row or column that instantiates N number of NAPs is 1/N for the last NAP in that direction, 1/(N-1) to next upstream NAP, and so on until the first instantiated NAP in the row or column. For example, if three NAPs are on a row, the westernmost NAP has priority every third cycle, the next upstream NAP has priority every second cycle, and the easternmost NAP always has priority as there are no further competing NAPs in the east-to-west direction. Both ACE and the simulation environment enforce the default arbitration value unless explicitly overridden by a user's value. For more information on the arbitration schedules, refer to the section "Speedster7t Network on Chip Primitives," in the Speedster7t IP Component Library User Guide (UG086).
Peripheral Ring of NoC with FIFO-based Arbitration
Transaction arbitration keeps data moving through the NoC without causing major congestion. For the peripheral portion of the NoC, a FIFO-based arbitration scheme is used, meaning transactions are handled on a first-come-first-served basis. If multiple transactions arrive on the same NoC clock cycle, a least-recently-serviced policy is used to order the transactions. This scheme guarantees that no endpoint is starved, and all transactions complete. The arbitration scheme in the peripheral portion of the NoC is not configurable. For more information refer to the Speedster7t Network on Chip User Guide (UG089).