Issue Description
ACE versions 8.0 and older use timing models that reflect optimistic hold time values for all LRAM input pins, except clock, and all BRAM inputs for BRAM FIFOs that are configured with parameter sync_mode=1. Additional hold margin must be added to the LRAM input pins and BRAM input pins when using the BRAM FIFO with parameter sync_mode=1 for proper functionality. This issue only affects LRAM blocks within the fabric and BRAM FIFO setting sync_mode to 1.
Note: This errata does not apply to ATE vectors.
Devices Affected
This errata applies to all Gen1, 16nm Speedcore eFPGA IP with LRAMs and BRAMs, including AC16tSC01HI01C.
Limitations
Additional hold margin is required on the LRAM input pins and will only affect the paths that terminate at an LRAM input pin. Similarly, additional hold margin is required on the BRAM inputs if using BRAM FIFO with sync_mode=1, and will only affect the paths that terminate at BRAM inputs. If these paths are limiting the performance of the design, then the resolution may have minimal impact to the performance and QoR of designs.
Resolution
This issue is fixed in ACE 8.1 design tools. Please contact Achronix for support.
Workaround
Customers planning to use older versions of ACE can use one of the two workarounds mentioned below:
1. Add Additional Hold Margin
Add an additional 40 ps hold margin to all inputs of each LRAM in the design (except clock) and 60 ps hold margin to all inputs of each BRAM FIFO with sync_mode=1.
set_min_delay 0.04 -to \[get_pins $LRAM_INSTANCE_NAME/*\]
set_min_delay 0.06 -to \[get_pins $BRAM_INSTANCE_NAME/*\]
The example script below can be used to find all LRAM instances and BRAM FIFO with sync_mode=1 instances in the design, and generate constraints which can be added to the .acxprj file:
########################################################
# Example script to generate LRAM delay constraints
# and BRAM delay constraints
# and add them to an existing ACE project file
# Modify as needed
########################################################
if { $argc != 1 } {
puts "The generate_ram_constraints.tcl script requires one ACXPRJ project file path argument."
puts "For example, ace -batch -script_file generate_ram_constraints.tcl -script_args /path/to/my/project.acxprj".
puts "Please try again."
exit 1
}
set prj_file [lindex $argv 0]
set sdc_file "[file rootname $prj_file]_ram_delay.sdc"
restore_project $prj_file
run_prepare
set lram_insts [find * -filter {@type=LRAM} -no_prefix -insts]
set outfile [open $sdc_file w]
puts $outfile "# RAM delay file generated from generate_ram_constraints.tcl"
foreach i $lram_insts {
puts $outfile "set_min_delay 0.04 -to \[get_pins \{$i/*\}\]"
}
# NOTE: this matches sync_mode == "1" and no other variations like "1'b1"
set bram_insts [find * -filter {@type=BRAMFIFOi && @attribute=sync_mode:1} -no_prefix -insts]
foreach i $bram_insts {
puts $outfile "set_min_delay 0.06 -to \[get_pins \{$i/*\}\]"
}
close $outfile
add_project_constraints $sdc_file
save_project
exit 0
2. Add Additional Hold Uncertainty
Add an additional hold uncertainty of 60 ps to the clocks in the design. For example, If the design uses two clocks, clk1 and clk2 and the current hold uncertainty is defined by $HOLD_MARGIN, add the constraints below to the SDC file:
set_clock_uncertainty -hold [$HOLD_MARGIN + 0.06] clk1
set_clock_uncertainty -hold [$HOLD_MARGIN + 0.06] clk2
Note: While this workaround may be easier to implement, it will add additional uncertainty to all paths and may affect the performance and QoR of the design.