Description

How are the GDDR6 interfaces numbered, and how do I utilize connectivity to NoC and direct-connect interfaces?

Answer

There are eight GDDR6 subsystems for a Speedster7t1500 FPGA device. Four subsystems sit on the west side of the device and four on the east side. The GDDR6 subsystems can interface with the FPGA core in two ways:

• NoC interface – Uses the network hierarchy to allow high-speed data flow between FPGA and peripheral interfaces.
• Direct-connect (DC) interface – Connects the memory controller directly to the core.

All eight GDDR6 subsystems support connectivity to the FPGA core using the NoC interface. However, only four subsystems can access the core via the direct connect interface. The following figure shows how these GDDR6 subsystems are numbered in our ACE software.

Figure: Speedster7t GDDR6 Subsystems Numbering in ACE

In the figure above the four subsystems namely GDDR6 #1, #2, #5 and #6 support the DC Interface connection.

Placement In ACE

The desired GDDR6 subsystem can be chosen in ACE while configuring the I/O ring. The 'Placement' parameter allows selection of one subsystem. For designs with multiple GDDR6 subsystem requirements, the user can clone an ACXIP file; each subsystem must placed at a different location.

Figure: GDDR6 subsystem IP Placement Selection in ACE

The figure below shows the I/O layout diagram when the placement is completed. In this example, GDDR6_2 has been selected and the I/O layout diagram highlights the chosen selection.

Figure: GDDR6 Subsystem I/O Layout Diagram in ACE

If the DCI connection is enabled for a GDDR6 subsystem, the PDC file generated contains all the AXI direct connect signals for the selected channels. Here is an example of how an AXI signal is placed for a GDDR6_2 channel 0 subsystem:

GDDR6 Placement in PDC File

#Place Channel 0 AXI signal
set_placement -fixed {p:gddr6_2_chan0_awready} {d:i_user_00_06_lut_02[20]}

Placement in Simulation

While accessing the GDDR6 subsystem via NoC, the AXI transactions use the NoC's global address map to read/write to a specific GDDR6 subsystem and corresponding channel. The table below shows the NoC global address map for GDDR6:

Table: NoC Global Address Map for GDDR6

 The following table shows the addressing scheme for transactions to the different GDDR6 subsystems, their respective control IDs, and the AC7t1500 device interface names to be connected to in the user RTL:

Table: GDDR6 Subsystem Control ID and Interface Name Map for NoC Interface

 Note: GDDR6 subsystems on west side uses odd addresses for channel 1, whereas the east side uses even addresses.

The user needs to set the address on their top-level RTL to access a GDDR6 subsystem. The address for a GDDR6 subsystem accessing the NoC is represented by the target ID and the memory address. The target ID comprises the nine most significant bits Addr[41:33]. The remaining bits Addr[32:0], represent the external memory address. So, to access GDDR6_5 channel 1, the target ID has to be set on the top RTL as follows:

Setting the GDDR6 target ID in RTL

parameter GDDR6_ADDR_ID = 9'b000000110;

Similar to NoC interface, for GDDR6 subsystems accessing the fabric via DC interface, the AXI transactions use the following address mapping for specific GDDR6 subsystems and their corresponding channels. The table below describes the mapping a user needs to set in their design:

Table: GDDR6 Subsystem AC7t1500 Interface Name Map for DCI